Harish Enumula Email
Sr. Staff Physical Design Engineer @ Sintegra Inc.
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Harish Enumula Work
- Sr. Staff Physical Design Engineer @ (February 2025 - Present)
- Sr. Staff Physical Design Engineer @ (February 2025 - Present)
- Senior Engineer @ (October 2024 - February 2025)
- Advanced Engineer @ (February 2023 - October 2024)
- Vendor @ (February 2023 - February 2025)
- VLSI Physical design engineer @ (October 2021 - January 2023)
- Physical Design Engineer @ (August 2018 - October 2021)
- Physical Design - Trainee @ (January 2018 - July 2018)
Harish Enumula Education
- SR University
Bachelor of Technology - BTech (electronics and communication engineering)
2014-2018
Harish Enumula Skills
- APR
- Analytical Skills
- Block level eco signoff
- C
- Cadence Encounter
- Cadence Virtuoso
- Cascading Style Sheets (CSS)
- Change Orders
- Clock Tree Synthesis
- Communication
- Engineering Change
- English
- Floorplanning
- Full chip timing analysis
- HTML
- HTML5
- LEC
- Layout Versus Schematic (LVS)
- Linux
- Low-power Design
- Microsoft Excel
- Microsoft Office
- Microsoft Word
- PDV
- PNR
- Perl
- Physical Design
- Place & Route
- Programming
- Research and Development (R&D)
- Scripting
- Static Timing Analysis
- Synopsys Primetime
- TCL
- Tapeout
- Timing Closure
- Unix
- VCLP
- signoff
Harish Enumula Summary
- Harish Enumula, is currently a Sr. Staff Physical Design Engineer at Sintegra Inc.. Harish Enumula brings experience from previous roles at Google, GUC and TSMC. Harish Enumula holds a 2014 - 2018 Bachelor of Technology - BTech in electronics and communication engineering @ SR University. With a robust skill set that includes APR, Analytical Skills, Block level eco signoff, C, Cadence Encounter and more. Harish Enumula has 2 emails on RocketReach.
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