Harisankar Aravindakshan's Location

San Jose, CA, US

Harisankar Aravindakshan's Work

Harisankar Aravindakshan's Education

  • Birla Institute of Technology and Science, Pilani

    Master of Technology

    2014 - 2016
  • Model Engineering College,Thrikkakkara

    Bachelor of Technology (Communication, Engineering)

    2005 - 2009

Harisankar Aravindakshan's Skills

  • Verilog
  • Analog Circuit Design
  • Analog
  • Semiconductors
  • RTL design
  • IC
  • ASIC
  • Debugging
  • Circuit Design
  • Static Timing Analysis

Harisankar Aravindakshan's Summary

Harisankar Aravindakshan, based in San Jose, CA, US, is currently a Senior Principal Validation Engineer at Astera Labs, bringing experience from previous roles at Astera Labs and Cadence Design Systems. Harisankar Aravindakshan holds a 2014 - 2016 Master of Technology @ Birla Institute of Technology and Science, Pilani. With a robust skill set that includes Verilog, Analog Circuit Design, Analog, Semiconductors, RTL design and more, Harisankar Aravindakshan contributes valuable insights to the industry. Harisankar Aravindakshan has 1 email and 2 mobile phone numbers on RocketReach.

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