Vivek Trivedi's Location
Santa Clara, CA, US
Vivek Trivedi's Work
- Associate VP Engineering @ Astera Labs
- mts @ XPliant
- Sr Staff Design Engg @ Cavium Inc
- MTS @ startup
- Staff Design Engineer @ Juniper Networks
- Staff Design Engg @ Intel Corporation
- Design Enginner @ Level One Communications
Vivek Trivedi's Education
- Stanford University
MSEE (Electrical Engg)
2002 - 2004 - Indian Institute of Technology, Kanpur
BSEE (Electrical Engg)
1992 - 1996
Vivek Trivedi's Skills
- BIST
- Roe
- Logic Design
- Logic Synthesis
- Perl
- RTL design
- ARM
- Microprocessors
- ASIC
- Timing
Vivek Trivedi's Summary
Vivek Trivedi, based in Santa Clara, CA, US, is currently a Associate VP Engineering at Astera Labs, bringing experience from previous roles at xpliant, Cavium Inc, startup and Juniper Networks. Vivek Trivedi holds a 2002 - 2004 MSEE in Electrical Engg @ Stanford University. With a robust skill set that includes BIST, Roe, Logic Design, Logic Synthesis, Perl and more, Vivek Trivedi contributes valuable insights to the industry. Vivek Trivedi has 2 emails and 1 mobile phone number on RocketReach.
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