DV Lead and RTL Designer @ Rivos (January 2022 - July 2023)
Senior Staff Engineer - Validation Technical Lead @ (May 2017 - January 2022)
Logic Design Engineer @ (January 2015 - May 2017)
Component Design Engineer @ (May 2010 - January 2015)
Research Assistant @ University of Illinois at Urbana-Champaign (September 2007 - May 2010)
Various Internships @ (January 2006 - August 2009)
Process Engineering Internship @ (May 2004 - September 2005)
Greg Lucas Education
University of Illinois Urbana-Champaign
Master of Science (M.S.) (Electrical and Computer Engineering)
2007-2009
Penn State University
Bachelor of Science (B.S.) (Electrical Engineering)
2003-2007
Greg Lucas Skills
Algorithms
C++
EDA
Linux
Perl
Python
Ruby
Static Timing Analysis
System on a Chip (SoC)
Universal Verification Methodology (UVM)
Validation
Verilog
Greg Lucas Summary
Greg Lucas, based in Fort Collins, CO, US, is currently a Senior Design Verification Engineer at NVIDIA. Greg Lucas brings experience from previous roles at Rivos and Intel Corporation. Greg Lucas holds a 2007 - 2009 Master of Science (M.S.) in Electrical and Computer Engineering @ University of Illinois Urbana-Champaign. With a robust skill set that includes Algorithms, C++, EDA, Linux, Perl and more. Greg Lucas has 2 emails and 1 mobile phone numbers on RocketReach.
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