ASIC Design and Verification training (ASIC Design and Verification)
2019-2020
North Maharashtra University
Master of Science (Electronics)
2017-2019
Gopal Dhangar Summary
Gopal Dhangar, based in Maharashtra, India, is currently a Senior Design Verification Engineer at Yoctozant Technologies. Gopal Dhangar brings experience from previous roles at Analog Devices and SiyaCon Technologies. Gopal Dhangar holds a 2019 - 2020 ASIC Design and Verification training in ASIC Design and Verification @ Excel VLSI Technologies. Gopal Dhangar has 1 emails on RocketReach.
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