2012 -
2021 Senior Principal Engineer, IC Design @
2006 -
2012 Senior Staff Engineer, ASIC Design @
2005 -
2006 Senior Staff Engineer, Logic Design @
1997 -
2005 Senior Staff Engineer, ASIC Design @
1995 -
1997 Member of Technical Staff, ASIC Design @
1992 -
1995 Member of Technical Staff, ASIC Design @
Gerald Cheung Education
Cornell University 1987
-
1992
Gerald Cheung Skills
ASIC
Verilog
Logic Design
Debugging
RTL design
Computer Architecture
Static Timing Analysis
Ethernet
Hardware
Public Speaking
Engineering
Integration
Computer Networking
Strategic Planning
Gerald Cheung Summary
Gerald Cheung, based in Palo Alto, CA, US, is currently a ASIC Design Engineer at Apple. Gerald Cheung brings experience from previous roles at Broadcom, Juniper Networks and Xsigo Systems. Gerald Cheung holds a 1987 - 1992 Cornell University. With a robust skill set that includes ASIC, Verilog, Logic Design, Debugging, RTL design and more. Gerald Cheung has 3 emails and 2 mobile phone numbers on RocketReach.
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