Ed Sayre Email & Phone Number
SI and PI Chip - System Co-Optimization Engineer @ NVIDIA
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Ed Sayre Location
- Underhill, VT, US
Ed Sayre Work
- SI and PI Chip - System Co-Optimization Engineer @ (January 2026 - Present)
- SI and PI Chip - System Co-Optimization Engineer @ (September 2023 - January 2026)
- Principal Engineer @ (November 2019 - August 2023)
- Senior Electrical Engineer @ (July 2015 - November 2019)
- Technical team lead, Senior Engineer @ (June 2006 - June 2015)
- Senior Signal and Power Integrity Engineer @ North East Systems Associates (April 1999 - June 2006)
- Semiconductor Test Engineer @ Digital Equipment Corporation (October 1990 - August 1993)
Ed Sayre Education
- Rensselaer Polytechnic Institute
Doctor of Philosophy - PhD (Electrical and Electronics Engineering)
1993-2000 - Rochester Institute of Technology
Master of Science (MS) (Electrical and Electronics Engineering)
1988-1990 - University of Massachusetts Amherst
Bachelor of Science (BS) (Electrcial Engineering)
1983-1988
Ed Sayre Skills
- ASIC
- Analog
- Cadence Voltus
- Characterization
- Circuit Design
- Debugging
- EDA
- FPGA
- HSPICE
- Hardware Architecture
- IC
- IR/EM analysis
- Integrated Circuit Design
- Physical Design
- Power Supplies
- Power Supply Design and analysis
- Power Supply Integrity
- Printed Circuit Board (PCB) Design
- Semiconductors
- Signal Integrity
- SoC
- Static Timing Analysis
- TCL
- Testing
- Timing Closure
- VLSI
- See 5+See Less
Ed Sayre Summary
- Ed Sayre, based in Underhill, VT, US, is currently a SI and PI Chip - System Co-Optimization Engineer at NVIDIA. Ed Sayre brings experience from previous roles at Groq, Marvell Semiconductor, GLOBALFOUNDRIES and IBM. Ed Sayre holds a 1993 - 2000 Doctor of Philosophy - PhD in Electrical and Electronics Engineering @ Rensselaer Polytechnic Institute. With a robust skill set that includes ASIC, Analog, Cadence Voltus, Characterization, Circuit Design and more. Ed Sayre has 1 emails and 1 mobile phone numbers on RocketReach.
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