David Chiou Email & Phone Number
Principal Engineer @ Marvell India
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David Chiou Location
- Cupertino, CA, US
David Chiou Work
- Principal Engineer @ (October 2012 - Present)
- Senior Staff Engineer @ (June 2005 - August 2012)
- Staff Engineer @ (June 2000 - June 2005)
- Senior Member of Technical Staff @ Sebring systems (November 1999 - June 2000)
- Member of Technical Staff @ (April 1993 - November 1999)
- Member of Technical Staff @ Symphony Laboratories (January 1991 - April 1993)
David Chiou Education
- Stony Brook University
Master of Science (Electrical Engineering)
- University of California - Davis
Pursuing PhD (Electrical Engineering)
David Chiou Skills
- ASIC
- Debugging
- FPGA
- Functional Verification
- Processors
- Integrated Circuit Design
- PCIe
- Simulations
- Testing
- Hardware
- X86
- Emulation
- Verilog
- SoC
- Semiconductors
- IC
- Application-Specific Integrated Circuits (ASIC)
- Field-Programmable Gate Arrays (FPGA)
- RTL Design
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
David Chiou Summary
- David Chiou, based in Cupertino, CA, US, is currently a Principal Engineer at Marvell. David Chiou brings experience from previous roles at Integrated Device Technology Inc, PLX Technology, Sebring systems and AMD. David Chiou holds a Master of Science in Electrical Engineering @ Stony Brook University. With a robust skill set that includes ASIC, Debugging, FPGA, Functional Verification, Processors and more. David Chiou has 2 emails and 2 mobile phone numbers on RocketReach.
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