David Chiou Email & Phone Number
Principal Engineer @ Marvell India
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David Chiou Location
- Cupertino, CA, US
David Chiou Work
- 2012 -now Principal Engineer @
- 2005 -2012 Senior Staff Engineer @
- 2000 -2005 Staff Engineer @
- 1999 -2000 Senior Member of Technical Staff @ Sebring systems
- 1993 -1999 Member of Technical Staff @
- 1991 -1993 Member of Technical Staff @ Symphony Laboratories
David Chiou Education
- Stony Brook University
Master of Science (Electrical Engineering)
- University of California - Davis
Pursuing PhD (Electrical Engineering)
David Chiou Skills
- ASIC
- Debugging
- FPGA
- Functional Verification
- Processors
- Integrated Circuit Design
- PCIe
- Simulations
- Testing
- Hardware
- X86
- Emulation
- Verilog
- SoC
- Semiconductors
- IC
- Application-Specific Integrated Circuits (ASIC)
- Field-Programmable Gate Arrays (FPGA)
- RTL Design
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
David Chiou Summary
- David Chiou, based in Cupertino, CA, US, is currently a Principal Engineer at Marvell. David Chiou brings experience from previous roles at Integrated Device Technology Inc, PLX Technology, Sebring systems and AMD. David Chiou holds a Master of Science in Electrical Engineering @ Stony Brook University. With a robust skill set that includes ASIC, Debugging, FPGA, Functional Verification, Processors and more. David Chiou has 2 emails and 2 mobile phone numbers on RocketReach.
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