Daniel Ferrão Email
IC Design Manager @ Chipus Microelectronics
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Daniel Ferrão Location
- State of Santa Catarina, Brazil
Daniel Ferrão Work
- IC Design Manager @ (November 2020 - Present)
- Digital IC Designer @ (April 2014 - November 2020)
- Physical IC Designer @ CEITEC (May 2008 - March 2014)
- Internship at clock design project @ FLA (September 2006 - March 2008)
- IC Designer @ CEITEC (May 2005 - September 2006)
Daniel Ferrão Education
- Federal University of Rio Grande do Sul
Master (Computer Science)
2003-2005 - Universidade Federal de Pelotas
BS (Computer Science - EDA for Timing Analysis)
1999-2003
Daniel Ferrão Skills
- Cadence Virtuoso
- Spectre
- CMOS
- ASIC
- EDA
- VLSI
- SoC
- IC
- Clock Tree Synthesis
- TCL
- Floorplanning
- Semiconductors
- Microelectronics
- Static Timing Analysis
- Perl
- Digital Design
- C
- Circuit Design
- Physical Design
- Silicon
- Power Management
- Physical Verification
- Power Analysis
- Timing Closure
- Backend
- cell characterization
- DRC
- LVS
- logic equivalent checking
- Integrated Circuit Design
- FPGA
- Place & Route
- Verilog
Daniel Ferrão Summary
- Daniel Ferrão, based in State of Santa Catarina, Brazil, is currently a IC Design Manager at Chipus Microelectronics. Daniel Ferrão brings experience from previous roles at Chipus Microelectronics, CEITEC and FLA. Daniel Ferrão holds a 2003 - 2005 Master in Computer Science @ Federal University of Rio Grande do Sul. With a robust skill set that includes Cadence Virtuoso, Spectre, CMOS, ASIC, EDA and more. Daniel Ferrão has 3 emails on RocketReach.
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