Dan Kist Email & Phone Number
Sr. Layout Engineer @ pSemi, A Murata Company
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Dan Kist Location
- San Diego, CA, US
Dan Kist Work
- Sr. Layout Engineer @ (March 2019 - Present)
- Layout Specialist @ (April 2014 - March 2019)
- Sr. Layout Designer @ (March 2012 - April 2014)
- Sr. Layout Engr. @ SMSC (December 2009 - January 2012)
- Mask Design Specialist @ (March 2002 - April 2009)
- Sr. Mask Designer @ (August 2000 - March 2002)
- Sr. Mask Designer @ (October 1998 - August 2000)
- Sr. Mask layout designer @ Ramtron International (January 1993 - January 1998)
- Sr. Mask Designer @ (May 1989 - September 1993)
- Mask Designer @ (January 1985 - January 1986)
- mask designer @ intel (January 1981 - January 1983)
Dan Kist Education
- DeVry University
Bachelor of Science - BS (Electrical and Electronics Engineering)
2014-2017 - DeVy Institute of Tech.
AASEET (Electronics Engineering Technology)
1979-1981
Dan Kist Skills
- BiCMOS
- DRC
- Floorplanning
- LVS
- Physical Verification
- Cadence Virtuoso
- CMOS
- Layout Versus Schematic (LVS)
- Integrated Circuits (IC)
- Mixed Signal
- Semiconductors
- System on a Chip (SoC)
- Cadence
- Circuit Design
- Integrated Circuit Design
- Low-power Design
- Mask Design
- PLL
- Power Management
- RF
- Semiconductor Industry
- SoC
- Virtuoso
- VLSI
- Technology
- Layout
- Mask
Dan Kist Summary
- Dan Kist, based in San Diego, CA, US, is currently a Sr. Layout Engineer at pSemi, A Murata Company. Dan Kist brings experience from previous roles at Analog Devices, Qualcomm - QCT, SMSC and Linear Technology. Dan Kist holds a 2014 - 2017 Bachelor of Science - BS in Electrical and Electronics Engineering @ DeVry University. With a robust skill set that includes BiCMOS, DRC, Floorplanning, LVS, Physical Verification and more. Dan Kist has 2 emails and 1 mobile phone numbers on RocketReach.
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