Dan Kist Location
- San Diego, CA, US
Dan Kist Work
- 2019 -now Sr. Layout Engineer @
- 2014 -2019 Layout Specialist @
- 2012 -2014 Sr. Layout Designer @
- 2009 -2012 Sr. Layout Engr. @ SMSC
- 2002 -2009 Mask Design Specialist @
- 2000 -2002 Sr. Mask Designer @
- 1998 -2000 Sr. Mask Designer @
- 1993 -1998 Sr. Mask layout designer @ Ramtron International
- 1989 -1993 Sr. Mask Designer @
- 1985 -1986 Mask Designer @
- 1981 -1983 mask designer @ intel
Dan Kist Education
- DeVry University
Bachelor of Science - BS (Electrical and Electronics Engineering)
2014-2017 - DeVy Institute of Tech.
AASEET (Electronics Engineering Technology)
1979-1981
Dan Kist Skills
- BiCMOS
- DRC
- Floorplanning
- LVS
- Physical Verification
- Cadence Virtuoso
- CMOS
- Layout Versus Schematic (LVS)
- Integrated Circuits (IC)
- Mixed Signal
- Semiconductors
- System on a Chip (SoC)
- Cadence
- Circuit Design
- Integrated Circuit Design
- Low-power Design
- Mask Design
- PLL
- Power Management
- RF
- Semiconductor Industry
- SoC
- Virtuoso
- VLSI
- Technology
- Layout
- Mask
Dan Kist Summary
- Dan Kist, based in San Diego, CA, US, is currently a Sr. Layout Engineer at pSemi, A Murata Company. Dan Kist brings experience from previous roles at Analog Devices, Qualcomm - QCT, SMSC and Linear Technology. Dan Kist holds a 2014 - 2017 Bachelor of Science - BS in Electrical and Electronics Engineering @ DeVry University. With a robust skill set that includes BiCMOS, DRC, Floorplanning, LVS, Physical Verification and more. Dan Kist has 2 emails and 1 mobile phone numbers on RocketReach.
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