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Dan Downs Location
United States
Dan Downs Work
CPU Verification Engineer @ (March 2018 - Present)
GPU Power Arch Engineer @ (November 2025 - Present)
Principal Engineer @ Errantly R&D (December 2015 - Present)
Staff CPU Verification Engineer @ (February 2011 - November 2015)
HW Engineer and Technical Writer @ (May 2010 - January 2011)
Principal Engineer @ Errantly R&D (June 2008 - April 2010)
Esterel Studio Consultant and Hardware Verification Engineer at TI @ (November 2006 - June 2008)
Hardware Engineer @ (April 2003 - November 2006)
DSP and Firmware Engineer (volunteer) @ MRC-Cognition and Brain Science Unit (May 2003 - October 2004)
Hardware Engineer @ (February 1999 - November 2002)
Hardware Modelling Engineer @ (January 1996 - December 1998)
Dan Downs Education
Lake Superior State University
BS (Electrical Engineering Technology)
1978-1982
Dan Downs Skills
Embedded Systems
ASIC
Hardware Architecture
FPGA
Verilog
VHDL
C
Debugging
Verification
Functional Verification
Cpu
Dan Downs Summary
Dan Downs, based in United States, is currently a CPU Verification Engineer at nVIDIA. Dan Downs brings experience from previous roles at nVIDIA, Errantly R&D, Qualcomm and Mentor Graphics. Dan Downs holds a 1978 - 1982 BS in Electrical Engineering Technology @ Lake Superior State University. With a robust skill set that includes Embedded Systems, ASIC, Hardware Architecture, FPGA, Verilog and more. Dan Downs has 1 emails on RocketReach.
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