Dan Downs's Location
United States
Dan Downs's Work
- CPU Verification Engineer @ NVIDIA
- Principal Engineer @ Errantly R&D
- Staff CPU Verification Engineer @ Qualcomm
- HW Engineer and Technical Writer @ Mentor Graphics
- Principal Engineer @ Errantly R&D
- Esterel Studio Consultant and Hardware Verification Engineer at TI @ Esterel Technologies
- Hardware Engineer @ MIPS
- DSP and Firmware Engineer (volunteer) @ MRC-Cognition and Brain Science Unit
- Hardware Engineer @ Arm
- Hardware Modelling Engineer @ IKOS Systems
Dan Downs's Education
- Lake Superior State University1978 - 1982
Dan Downs's Skills
- Embedded Systems
- ASIC
- Hardware Architecture
- FPGA
- Verilog
- VHDL
- C
- Debugging
- Verification
- Functional Verification
Dan Downs's Summary
Dan Downs, based in United States, is currently a CPU Verification Engineer at nVIDIA, bringing experience from previous roles at Errantly R&D, Qualcomm and Mentor Graphics. Dan Downs holds a 1978 - 1982 Lake Superior State University. With a robust skill set that includes Embedded Systems, ASIC, Hardware Architecture, FPGA, Verilog and more, Dan Downs contributes valuable insights to the industry. Dan Downs has 2 emails on RocketReach.
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