Dan Downs Email & Phone Number
CPU Verification Engineer @ NVIDIA
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Dan Downs Location
- United States
Dan Downs Work
- 2018 -now CPU Verification Engineer @
- 2025 -now GPU Power Arch Engineer @
- 2015 -now Principal Engineer @ Errantly R&D
- 2011 -2015 Staff CPU Verification Engineer @
- 2010 -2011 HW Engineer and Technical Writer @
- 2008 -2010 Principal Engineer @ Errantly R&D
- 2006 -2008 Esterel Studio Consultant and Hardware Verification Engineer at TI @
- 2003 -2006 Hardware Engineer @
- 2003 -2004 DSP and Firmware Engineer (volunteer) @ MRC-Cognition and Brain Science Unit
- 1999 -2002 Hardware Engineer @
- 1996 -1998 Hardware Modelling Engineer @
Dan Downs Education
- Lake Superior State University
BS (Electrical Engineering Technology)
1978-1982
Dan Downs Skills
- Embedded Systems
- ASIC
- Hardware Architecture
- FPGA
- Verilog
- VHDL
- C
- Debugging
- Verification
- Functional Verification
- Cpu
Dan Downs Summary
- Dan Downs, based in United States, is currently a CPU Verification Engineer at nVIDIA. Dan Downs brings experience from previous roles at nVIDIA, Errantly R&D, Qualcomm and Mentor Graphics. Dan Downs holds a 1978 - 1982 BS in Electrical Engineering Technology @ Lake Superior State University. With a robust skill set that includes Embedded Systems, ASIC, Hardware Architecture, FPGA, Verilog and more. Dan Downs has 1 emails on RocketReach.
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