Curtis Webster Location
- San Ramon, CA, US
Curtis Webster Work
- 2015 - now Asic Digital Design Manager @
- 2014 - 2015 Senior Engineering Manager @
- 2013 - 2014 Senior Design Manager @
- 2006 - 2013 Principal Engineer @
- 2005 - 2006 Asic Design Contractor @
- 2003 - 2005 Senior Staff Asic Engineer @
- 2000 - 2003 Senior Staff Asic Engineer @ Rhapsody Networks
- 1999 - 2000 Senior Engineer @
- 1990 - 1992 Electronic Design Engineer @
- 1987 - 1990 Electronic Engineer @ Mirage Systems
- now Electronic Design Engineer @
Curtis Webster Education
- Santa Clara University
Master Of Science (Engineering)
1996 - 2001 - Weber State University
Bachelor Of Science (Engineering)
1983 - 1987
Curtis Webster Skills
- RTL design
- DDR
- Semiconductors
- Ddr Phy Ip
- Debugging
- Technical Staff Management
- ASIC
- Memory Interfaces
- Static Timing Analysis
- Timing Closure
- FPGA
- SoC
- Verilog
- SRAM
- VLSI
- EDA
- Perl Script
- Logic Synthesis
- Functional Verification
- IC
Curtis Webster Summary
- Curtis Webster, based in San Ramon, CA, US, is currently a Asic Digital Design Manager at Synopsys Inc. Curtis Webster brings experience from previous roles at Cadence Design Systems, Lsi, an Avago Technologies Company and Pro Unlimited. Curtis Webster holds a 1996 - 2001 Master Of Science in Engineering @ Santa Clara University. With a robust skill set that includes RTL design, DDR, Semiconductors, Ddr Phy Ip, Debugging and more. Curtis Webster has 2 emails and 1 mobile phone numbers on RocketReach.
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