Ching Yu Location
- Sunnyvale, CA, US
Ching Yu Work
- 2011 - now Senior Principal Engineer @
- 2010 - 2011 Co-Founder, Vice President of Engineering @
- 2008 - 2009 MTS @
- 2007 - 2008 Principal Architect @
- 2003 - 2006 Vice President Asic and Silicon Engineering @
- 1999 - 2002 Director of Asic Engineering @ Virata Globespanvirata
- 1988 - 1999 Design Engineer and Design Manager @
Ching Yu Education
- Santa Clara University
Master of Business Administration (Marketing, Organizational Leadership)
- University of California, Los Angeles
Bachelor of Science (Electronics Engineering)
Ching Yu Skills
- RTL design
- SystemVerilog
- Semiconductors
- Physical Design
- Mixed Signal
- Embedded Systems
- ASIC
- Hardware Architecture
- Static Timing Analysis
- CMOS
- Processors
- FPGA
- Low Power Design
- SoC
- Verilog
- VLSI
- EDA
- System Architecture
- IC
Ching Yu Summary
- Ching Yu, based in Sunnyvale, CA, US, is currently a Senior Principal Engineer at Intel Corporation. Ching Yu brings experience from previous roles at Xingtera, Dust Networks and Level 5 Networks. Ching Yu holds a Master of Business Administration in Marketing, Organizational Leadership @ Santa Clara University. With a robust skill set that includes RTL design, SystemVerilog, Semiconductors, Physical Design, Mixed Signal and more. Ching Yu has 2 emails and 2 mobile phone numbers on RocketReach.
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