Chen Email
Senior Analog Design Engineer @ Marvell India
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Chen Location
- United States
Chen Work
- 2012 -now Senior Analog Design Engineer @
- 2011 -2011 Power Management Ic Design Engineering Intern @
- 2010 -2011 Graduate School Research at Analog and Mixed Signal Center @
- now Senior Analog Design Engineer at Marvell Semiconductor @
Chen Education
- Texas A&M University
Master of Engineering (Electrical Engineering, Engineering, Design)
2009-2011 - Shanghai Jiao Tong University
Bachelor of Science
2005-2009
Chen Skills
- HSpice
- Cadence Virtuoso
- Matlab
- Simulink
- Verilog
- C++
- Analog
- Analog Circuit Design
- CMOS
- Integrated Circuit Design
- PLL
- Mixed Signal
- VLSI
- PCB design
- RF
- SPICE
- Phase-Locked Loop (PLL)
- Cadence Spectre
- Debugging
- Low-power Design
- Electronics
- SoC
- IC
- Circuit Design
- Integrated Circuit
- Low Power Design
- Phase Locked Loop Pll
- Phase Locked Loop
Chen Summary
- Chen, based in United States, is currently a Senior Analog Design Engineer at Marvell Semiconductor. Chen brings experience from previous roles at Qualcomm, Texas A&m University and Marvell Semiconductor. Chen holds a 2009 - 2011 Master of Engineering in Electrical Engineering, Engineering, Design @ Texas A&M University. With a robust skill set that includes HSpice, Cadence Virtuoso, Matlab, Simulink, Verilog and more. Chen has 2 emails on RocketReach.
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