Chao Email
System Level Cache Design Engineer @ NVIDIA
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Chao Location
- California, United States
Chao Work
- System Level Cache Design Engineer @ (March 2024 - Present)
- CPU Core Engineer @ (July 2018 - February 2024)
Chao Education
- University of Michigan
Master's degree (VLSI)
2016-2018 - Beihang University
Bachelor's degree (Electrical and Electronics Engineering)
2012-2016
Chao Skills
- Application-Specific Integrated Circuits (ASIC)
- C
- C++
- Cadence
- Cadence Encounter
- Cadence Virtuoso
- Computer Architecture
- DVE
- Design Compiler
- Digital Circuit Design
- LabVIEW
- Linux
- Matlab
- NC-Verilog
- Perl
- Physical Design
- SPICE
- Shell
- Synopsys
- Synopsys tools
- SystemVerilog
- Tcl
- UVM
- VCS
- Verilog
- Very-Large-Scale Integration (VLSI)
Chao Summary
- Chao, based in California, United States, is currently a System Level Cache Design Engineer at NVIDIA. Chao brings experience from previous roles at Apple. Chao holds a 2016 - 2018 Master's degree in VLSI @ University of Michigan. With a robust skill set that includes Application-Specific Integrated Circuits (ASIC), C, C++, Cadence, Cadence Encounter and more. Chao has 1 emails on RocketReach.
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