Blustac Information

Auviz Systems is an Independent Software Vendor (ISV) that accelerates algorithms for the Data Center & Embedded Devices. We provide Middleware IP, Custom Accelerators and Services for application developers that require higher performance at lower power. Auviz Middleware IP (AuvizCV, AuvizLA and AuvizDNN) solves the problem of achieving good Quality of Results (QOR, i.e. performance, area, latency) from OpenCL and High Level Synthesis without having to know the details of the underlying Hardware Architecture. Targeting FPGA’s, Auviz Middleware enables software developers to program using their existing methodology - C/C++ with an OpenCL platform model. Auviz expertise in Machine Learning, Vision Algorithms, FPGA implementation, software development and applications uniquely positions us to help close the ‘programming gap’ for FPGA’s Auviz Middleware IP is highly optimized for Xilinx Series 7 FPGAs. The Middleware IP is available as synthesizable, C functions for HLS users, OpenCL for Embedded developers, or IP Integrator blocks for traditional RTL users. Customers on different design flows can use Auviz IP to design and get to market faster. Creating end applications using Auviz Systems™ Middleware IP is easy because we have done the hard work of optimizing algorithms on the FPGA already! It is now as simple as calling the functions from your C/C++ program using our API. You can use the OpenCL platform model to call the API from your embedded code, or use HLS to call the API for a more traditional flow. Check out some examples below, or get in touch with us to get more specific. Located in Silicon Valley, USA and Hyderabad, India, Auviz Systems is also a Xilinx Alliance Partner.