Ashish Mehra's Location

San Francisco, California, United States

Ashish Mehra's Work

Ashish Mehra's Education

  • Indian Institute of Technology, Kharagpur

    Masters (Vlsi Design)

    2000 - 2002
  • G.B. Pant Engineering College

    Bachelor of Technology (Electronics, Engineering, Communications)

    1996 - 2000

Ashish Mehra's Skills

  • EDA
  • VLSI
  • Timing Closure
  • ASIC
  • SoC
  • Static Timing Analysis
  • IC
  • Clock Tree Synthesis
  • Physical Design
  • Verilog

Ashish Mehra's Summary

Ashish Mehra, based in San Francisco, California, United States, is currently a Senior Group Director, Product Engineering at Cadence Design Systems, bringing experience from previous roles at Cadence Design Systems, Synopsys Inc and Magma Design Automation. Ashish Mehra holds a 2000 - 2002 Masters in Vlsi Design @ Indian Institute of Technology, Kharagpur. With a robust skill set that includes EDA, VLSI, Timing Closure, ASIC, SoC and more, Ashish Mehra contributes valuable insights to the industry. Ashish Mehra has 4 emails and 1 mobile phone number on RocketReach.

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