Aparna Mohan Location
- Austin, TX, US
Aparna Mohan Work
- 2026 -now Design Verification Engineer @
- 2025 -now Program Committee Member : Test, Verification, and Security Track @ 43rd IEEE International Conference on Computer Design (ICCD 2025)
- 2025 -now Technical Program Committee Member @ 7th ACM/IEEE International Symposium on Machine Learning for CAD
- 2025 -now Technical Program Committee Member : Engineering Papers and Research Track @ DVCon Europe
- 2025 -now Mentor @
- 2025 -now Technical Program Committee Member @
- 2023 -2026 Design Verification Engineer @
- 2017 -2020 Senior Verification Engineer @
- 2023 -2023 Senior Staff Verification Engineer @
- 2020 -2023 Staff Verification Engineer @
- 2014 -2017 Design Verification Engineer @
- 2013 -2014 Graduate Research Assistant @
- 2013 -2013 Mixed Signal IC Design Intern @
- 2013 -2013 Graduate Leadership Development Series Participant @
- 2012 -2013 Academic Assistant for Geology I:Physical (MEA 101) @
- 2010 -2012 Scientist and Engineer,Laboratory for Electro-Optics Systems @
- 2010 -2010 Associate Software Engineer @
- 2009 -2009 Summer Intern @
Aparna Mohan Education
- North Carolina State University
Master of Science (M.S.) (Electrical Engineering)
2012-2014 - College of Engineering Trivandrum 2006-2010
- St.Thomas Central School 1994-2004
Aparna Mohan Skills
- Formal Verification
- Assertion Based Verification
- Team Leadership
- System on a Chip (SoC)
- Universal Verification Methodology (UVM)
- SystemVerilog
- Application-Specific Integrated Circuits (ASIC)
- Circuit Design
- Power Electronics
- FPGA
- Very-Large-Scale Integration (VLSI)
- Debugging
- Matlab
- VHDL
- C++
- Pspice
- Verilog
- Visual Basic
- C
- Cadence Virtuoso
- 8051 Microcontroller
- Integrated Circuit Design
- Xilinx ISE
- MSP430
- FPGA designing
- Calibre
- Functional Verification
- Integrated Circuit
- Design
- Research
- Verification
Aparna Mohan Summary
- Aparna Mohan, based in Austin, TX, US, is currently a Design Verification Engineer at NVIDIA. Aparna Mohan brings experience from previous roles at 43rd IEEE International Conference on Computer Design (ICCD 2025), 7th ACM/IEEE International Symposium on Machine Learning for CAD, DVCon Europe and Rewriting the Code. Aparna Mohan holds a 2012 - 2014 Master of Science (M.S.) in Electrical Engineering @ North Carolina State University. With a robust skill set that includes Formal Verification, Assertion Based Verification, Team Leadership, System on a Chip (SoC), Universal Verification Methodology (UVM) and more. Aparna Mohan has 3 emails and 2 mobile phone numbers on RocketReach.
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