Aparna Mohan Email & Phone Number
Design Verification Engineer @ NVIDIA
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Aparna Mohan Location
- Austin, TX, US
Aparna Mohan Work
- Design Verification Engineer @ (February 2026 - Present)
- Program Committee Member : Test, Verification, and Security Track @ 43rd IEEE International Conference on Computer Design (ICCD 2025) (May 2025 - Present)
- Technical Program Committee Member @ 7th ACM/IEEE International Symposium on Machine Learning for CAD (May 2025 - Present)
- Technical Program Committee Member : Engineering Papers and Research Track @ DVCon Europe (April 2025 - Present)
- Mentor @ (April 2025 - Present)
- Technical Program Committee Member @ (April 2025 - Present)
- Design Verification Engineer @ (June 2023 - January 2026)
- Senior Staff Verification Engineer @ (March 2023 - June 2023)
- Staff Verification Engineer @ (April 2020 - March 2023)
- Senior Verification Engineer @ (April 2017 - March 2020)
- Design Verification Engineer @ (July 2014 - March 2017)
- Graduate Research Assistant @ (August 2013 - June 2014)
- Mixed Signal IC Design Intern @ (May 2013 - August 2013)
- Graduate Leadership Development Series Participant @ (February 2013 - May 2013)
- Academic Assistant for Geology I:Physical (MEA 101) @ (September 2012 - April 2013)
- Scientist and Engineer,Laboratory for Electro-Optics Systems @ (September 2010 - June 2012)
- Associate Software Engineer @ (June 2010 - July 2010)
- Summer Intern @ (March 2009 - April 2009)
Aparna Mohan Education
- North Carolina State University
Master of Science (M.S.) (Electrical Engineering)
2012-2014 - College of Engineering Trivandrum
B.Tech (Applied Electronics and Instrumentation)
2006-2010 - St.Thomas Central School
10,10+2 (Physics,Maths,Chemistry,Computer,English)
1994-2004
Aparna Mohan Skills
- Formal Verification
- Assertion Based Verification
- Team Leadership
- System on a Chip (SoC)
- Universal Verification Methodology (UVM)
- SystemVerilog
- Application-Specific Integrated Circuits (ASIC)
- Circuit Design
- Power Electronics
- FPGA
- Very-Large-Scale Integration (VLSI)
- Debugging
- Matlab
- VHDL
- C++
- Pspice
- Verilog
- Visual Basic
- C
- Cadence Virtuoso
- 8051 Microcontroller
- Integrated Circuit Design
- Xilinx ISE
- MSP430
- FPGA designing
- Calibre
- Functional Verification
- Integrated Circuit
- Design
- Research
- Verification
Aparna Mohan Summary
- Aparna Mohan, based in Austin, TX, US, is currently a Design Verification Engineer at NVIDIA. Aparna Mohan brings experience from previous roles at 43rd IEEE International Conference on Computer Design (ICCD 2025), 7th ACM/IEEE International Symposium on Machine Learning for CAD, DVCon Europe and Rewriting the Code. Aparna Mohan holds a 2012 - 2014 Master of Science (M.S.) in Electrical Engineering @ North Carolina State University. With a robust skill set that includes Formal Verification, Assertion Based Verification, Team Leadership, System on a Chip (SoC), Universal Verification Methodology (UVM) and more. Aparna Mohan has 2 emails and 1 mobile phone numbers on RocketReach.
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