Anuj Panwar Email & Phone Number
Senior ASIC Design Engineer @ NVIDIA
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Anuj Panwar Location
- California, United States
Anuj Panwar Work
- Senior ASIC Design Engineer @ (February 2024 - Present)
- ASIC Design Engineer @ (February 2022 - February 2024)
- Circuit Design Engineer @ (August 2019 - February 2022)
- SoC Design Engineer @ (June 2018 - August 2019)
- Graduate Technical Intern @ (February 2018 - May 2018)
- Intern @ (May 2017 - August 2017)
Anuj Panwar Education
- University of Southern California
Master of Science - MS (Electrical and Electronics Engineering)
2017-2018 - Delhi Technological University
Bachelor's degree (Electrical, Electronics and Communications Engineering)
2010-2014
Anuj Panwar Skills
- Altera Quartus
- C
- CMOS
- Cadence Virtuoso
- Calibre Designrev
- Calibre PERC
- Circuit
- Circuit Design
- Conformal LEC
- Custom WaveView
- CustomSim Circuit Check
- Dc Compiler
- Digital Electronics
- Digital Signal Processing
- Eclipse
- Embedded Systems
- Finesim
- HSIM
- HSPICE
- Keil
- Linux
- Logic Synthesis
- Matlab
- Microarchitecture
- Microcontrollers
- Microsemi Libero
- Python
- RTL Design
- SRAM
- Semiconductors
- Synopsys Primetime
- Unix
- VHDL
- VLSI
- Verilog
- Xilinx
- mbed compiler
- nWave
- system verilog
Anuj Panwar Summary
- Anuj Panwar, based in California, United States, is currently a Senior ASIC Design Engineer at NVIDIA. Anuj Panwar brings experience from previous roles at Apple, Intel Corporation and Synopsys Inc. Anuj Panwar holds a 2017 - 2018 Master of Science - MS in Electrical and Electronics Engineering @ University of Southern California. With a robust skill set that includes Altera Quartus, C, CMOS, Cadence Virtuoso, Calibre Designrev and more. Anuj Panwar has 1 emails and 1 mobile phone numbers on RocketReach.
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