Amit Rane Email & Phone Number
Distinguished Engineer @ Astera Labs
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Amit Rane Location
- Santa Clara, CA, US
Amit Rane Work
- Distinguished Engineer @ (April 2025 - Present)
- Analog IC Design Leader (SMTS) @ (January 2007 - April 2025)
- Analog IC Design Manager responsible for USB and 56Gbps+ PAM4 products @ (January 2007 - April 2025)
- Design Manager @ (January 1998 - January 2007)
Amit Rane Education
- University of California, Berkeley
Management
2011-2011 - UCLA
MSEE
- Veermata Jijabai Technological Institute (VJTI)
Bachelor of Engineering - BE
Amit Rane Skills
- ADCs
- ASIC
- Adaptation
- Analog
- Analog Circuit Design
- Analog Design
- Artificial Intelligence (AI)
- Bandgap References
- BiCMOS
- CDR
- CMOS
- CTLE
- DACS
- Digital Signal Processing
- Entrepreneurship
- Ethernet
- High Speed Design
- IC
- Integrated Circuit Design
- Low-power Design
- Mixed Signal
- Mixed-Signal IC Design
- Optical Fiber
- PAM4
- PCIe
- Phase-Locked Loop (PLL)
- Product Development
- Product Requirement Definition
- RF
- RF Design
- SDI
- Semiconductors
- SerDes
- Serial ATA (SATA)
- Signal Integrity
- SoC
- Speech Processing
- USB
- Veriloga
- Voltage Regulator
Amit Rane Summary
- Amit Rane, based in Santa Clara, CA, US, is currently a Distinguished Engineer at Astera Labs. Amit Rane brings experience from previous roles at Texas Instruments and Intel. Amit Rane holds a 2011 - 2011 Management @ University of California, Berkeley. With a robust skill set that includes ADCs, ASIC, Adaptation, Analog, Analog Circuit Design and more. Amit Rane has 2 emails and 1 mobile phone numbers on RocketReach.
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