Alexander Shapiro's Location
Beaverton, OR, US
Alexander Shapiro's Work
- SoC Performance Architect @ Intel Corporation
- SRAM and RF Memory Compiler Platform Engineer @ Intel Corporation
- SRAM and RF Memory Compiler Post-Si Test @ Intel Corporation
- Research Assistant @ University of Rochester
- Teaching Assistant, Department of Electrical and Computer Engineering @ University of Rochester
- Memory IP Group Intern - Intel Custom Foundry @ Intel Corporation
- Circuits Design Group Intern @ Qualcomm
- Pre-Sillicon Emulation Engineer @ Intel Corporation
- Clock Distribution Engineer (part time) @ IBM
- Backend Team Intern @ IBM
Alexander Shapiro's Education
- University of Rochester
Alexander Shapiro's Skills
- VLSI
- Matlab
- TCL
- ASIC
- C
- Cadence Virtuoso
- FPGA
- Integrated Circuit Design
- Near Threshold Circuits
- Low Power Design
Alexander Shapiro's Summary
Alexander Shapiro, based in Beaverton, OR, US, is currently a SoC Performance Architect at Intel Corporation, bringing experience from previous roles at Intel Corporation and University of Rochester. Alexander Shapiro holds a University of Rochester. With a robust skill set that includes VLSI, Matlab, TCL, ASIC, C and more, Alexander Shapiro contributes valuable insights to the industry. Alexander Shapiro has 2 emails on RocketReach.
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