Aditya Devarakonda Email & Phone Number
Senior Engineering Manager (Design Verification) @ NXP Semiconductors
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Aditya Devarakonda Location
- Phoenix, AZ, US
Aditya Devarakonda Work
- 2022 - now Senior Engineering Manager (Design Verification) @
- 2021 - 2022 Verification Team Lead @
- 2019 - 2021 Verification Team Lead @
- 2016 - 2019 Senior Member of Technical Staff @
- 2015 - 2016 Digital Design and Verification Lead @
- 2014 - 2015 Digital Design and Verification Lead @
- 2012 - 2014 Design and Verification @
- 2010 - 2012 Senior Design Engineer @
- 2007 - 2010 Design Engineer @
- 2006 - 2007 Product Engineer @
- 2004 - 2006 Research Assistant @
Aditya Devarakonda Education
- Utah State University
Master of Science (Electrical Engineering)
2003 - 2006 - Jawaharlal Nehru Technological University
Bachelor of Technology (Electronics and Communication Engineering)
1999 - 2003
Aditya Devarakonda Skills
- Cadence Virtuoso
- Analog Circuit Design
- SPICE
- RTL design
- Analog
- ASIC
- Spectre
- VLSI
- Verilog
- Integrated Circuit Design
- Supervision
- Integrated Circuits Ic
- Mixed Signal
- CMOS
- FPGA
- SoC
- VHDL
- EDA
- ModelSim
- Primetime
- Synopsys tools
- Semiconductors
- Design
- Static Timing Analysis
- IC
- Integrated Circuits
Aditya Devarakonda Summary
- Aditya Devarakonda, based in Phoenix, AZ, US, is currently a Senior Engineering Manager (Design Verification) at NXP Semiconductors. Aditya Devarakonda brings experience from previous roles at Renesas Electronics, Dialog Semiconductor, Maxim Integrated and NXP Semiconductors. Aditya Devarakonda holds a 2003 - 2006 Master of Science in Electrical Engineering @ Utah State University. With a robust skill set that includes Cadence Virtuoso, Analog Circuit Design, SPICE, RTL design, Analog and more. Aditya Devarakonda has 3 emails and 2 mobile phone numbers on RocketReach.
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