Abdul Rafay Email & Phone Number
Sr. Principal Engineer, Design Verification @ Astera Labs
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Abdul Rafay Location
- Mississauga, ON, CA
Abdul Rafay Work
- Sr. Principal Engineer, Design Verification @ (February 2025 - Present)
- Principal Engineer, Design Verification @ (April 2022 - February 2025)
- Member Of Technical Staff: Silicon Design Verification @ (August 2020 - April 2022)
- Sr. Design Verification Engineer @ (February 2018 - August 2020)
- Graduate Intern, ASIC Digital Design and Verification @ (October 2017 - January 2018)
- Research Assistant at iRadio Lab @ (May 2016 - September 2017)
- Implementation Coordinator @ (December 2014 - April 2016)
- Project Engineer (3G) @ CMPak (August 2014 - November 2014)
- RAN Supervisor @ (August 2013 - June 2014)
- Hardware Design Engineer @ (March 2012 - May 2013)
- Development Engineer @ (June 2011 - February 2012)
Abdul Rafay Education
- University of Calgary
Master’s Degree (Electrical and Computer Engineering)
2016-2018 - NED University of Engineering and Technology
BE (Electronics)
2008-2011 - The Fahims School System
GCE A Level (Pre-Eng)
2005-2007 - St. Michael's Convent
GCE O Level (Pre-Eng)
2000-2005
Abdul Rafay Skills
- ARM
- AXI
- Algorithms
- Application-Specific Integrated Circuits (ASIC)
- Architecture
- Assertion Based Verification
- C++ Language
- Cadence
- Communication Skills
- Computer Simulations
- Data Structures
- Debugging
- Defining Requirements
- Digital Logic
- Electronics
- Embedded C
- Embedded Systems
- FPGA
- Formal Verification
- Functional Testing
- Functional Verification
- Gigabit Ethernet
- Hardware Emulation
- Hardware Verification
- I2C
- Integrated Circuit Design
- Leadership
- Linux
- Logic Design
- Management
- Matlab
- Methodology
- Microcontrollers
- Oral Communication
- PCB design
- PCIe
- Perl Script
- Portable Stimulus Standard
- Presentations
- Problem Solving
- Productivity Improvement
- Project Management
- Python (Programming Language)
- Reporting & Analysis
- Strategic Thinking
- SystemVerilog
- TCL
- Team Management
- Test Environment Setup
- Transmission
- UNR
- UPF
- Universal Verification Methodology (UVM)
- Verilog
Abdul Rafay Summary
- Abdul Rafay, based in Mississauga, ON, CA, is currently a Sr. Principal Engineer, Design Verification at Astera Labs. Abdul Rafay brings experience from previous roles at Astera Labs, AMD, Xilinx and Synopsys Inc. Abdul Rafay holds a 2016 - 2018 Master’s Degree in Electrical and Computer Engineering @ University of Calgary. With a robust skill set that includes ARM, AXI, Algorithms, Application-Specific Integrated Circuits (ASIC), Architecture and more. Abdul Rafay has 1 emails and 1 mobile phone numbers on RocketReach.
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