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Aayush Pathak Location
California, United States
Aayush Pathak Work
2025 -now Sr. Product Manager @
2022 -now Advisory Council Member @
2022 -2025 Senior Product Engineer @
2023 -2024 Business Strategy Consultant @
2020 -2022 Sr. Product Architecture Engineer @
2016 -2020 Silicon Architecture Engineer @
2015 -2017 CEO, Co-Founder @ JARVIS-WEM
2016 -2016 Design Engineering Intern @
2013 -2014 Member of Technical Staff @
2011 -2013 Product Engineer I @
2010 -2011 Project Engineer @
2008 -2010 Business Development Consultant @ SVE (India) Pvt. Ltd
2009 -2009 Graduate Student Intern @ Power Grid Corporation of India Ltd
Aayush Pathak Education
Somerville School - India 1999-2006
The University of Chicago Booth School of Business
University of Southern California
Amity University
Harvard Business School Online
Stanford University
Indian Institute of Technology, Delhi
Aayush Pathak Skills
Physical Design
DFT
Front End Verification using Verilog
VLSI
Verilog
Verification
RTL coding
SystemVerilog
Bluetooth
Static Timing Analysis
Cadence
Functional Verification
Formal Verification
VHDL
EDA
FPGA
RTL design
TCL
ASIC
Timing Closure
Logic Synthesis
Integrated Circuit Design
DRC
NCSim
ModelSim
Primetime
Debugging
Physical Verification
Cadence Virtuoso
LVS
Data Validation
PCB design
Intel
Software
CPU design
Mentor Graphics
Very Large Scale Integration Vlsi
Architecture
Very Large Scale Integration
Aayush Pathak Summary
Aayush Pathak, based in California, United States, is currently a Sr. Product Manager at NVIDIA. Aayush Pathak brings experience from previous roles at Harvard Business Review, Microsoft, Grow Movement and Intel Corporation. Aayush Pathak holds a 1999 - 2006 Somerville School - India. With a robust skill set that includes Physical Design, DFT, Front End Verification using Verilog, VLSI, Verilog and more. Aayush Pathak has 3 emails and 1 mobile phone numbers on RocketReach.
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