Zhigang Wu's Location
Yokohama, Kanagawa, JP
Zhigang Wu's Work
- Principal Design Engineer @ ChangXin Memory Technologies, Inc.
- Assistant Technical Director @ Yangtze Memory Technologies
- Staff Physical Design Engineer @ Western Digital
- Senior AE @ Magma Design Automation
- Senior CAD Engineer @ Cadence Design Systems
- Project leader @ KLA
Zhigang Wu's Education
- Yamagata University
Master's degree (Information Technology)
Zhigang Wu's Skills
- Simulations
- Semiconductors
- Mixed Signal
- Analog
- ASIC
- Physical Design
- FPGA
- SoC
- Verilog
- EDA
Zhigang Wu's Summary
Zhigang Wu, based in Yokohama, Kanagawa, JP, is currently a Principal Design Engineer at ChangXin Memory Technologies, Inc., bringing experience from previous roles at Yangtze Memory Technologies Inc., Western Digital, Magma Design Automation and Cadence Design Systems. Zhigang Wu holds a Master's degree in Information Technology @ Yamagata University. With a robust skill set that includes Simulations, Semiconductors, Mixed Signal, Analog, ASIC and more, Zhigang Wu contributes valuable insights to the industry. Zhigang Wu has 2 emails on RocketReach.
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