Zhaoxin Gu Email & Phone Number
Senior ASIC Design Engineer @ NVIDIA
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Zhaoxin Gu Location
- California, United States
Zhaoxin Gu Work
- Senior ASIC Design Engineer @ (October 2023 - Present)
- ASIC Design Verification Engineer @ (June 2019 - October 2023)
- Embedded System Engineer Intern ( Signal Processing and Optimization team) @ (May 2017 - August 2017)
Zhaoxin Gu Education
- University of California, Berkeley
Master of Engineering - MEng (EECS)
2018-2019 - University of Illinois Urbana-Champaign
Bachelor of Science - BS (Electrical Engineering)
2014-2018
Zhaoxin Gu Skills
- C++
- C
- OpenCL
- Linux
- Microsoft Office
- Microsoft Excel
- Microsoft Word
- PowerPoint
- Microsoft Windows
- Matlab
- Python
- Microsoft Outlook
- Problem Solving
- Team work
- SystemVerilog
- SystemVerilog Assertion
- Digital Signal Processing
- CUDA
- Language：English， Chinese
- LC-3 Assembly
- RTL Design
- Verilog
- Digital Designs
- REGEX
- Regular Expressions
Zhaoxin Gu Summary
- Zhaoxin Gu, based in California, United States, is currently a Senior ASIC Design Engineer at NVIDIA. Zhaoxin Gu brings experience from previous roles at Apple and Illumina. Zhaoxin Gu holds a 2018 - 2019 Master of Engineering - MEng in EECS @ University of California, Berkeley. With a robust skill set that includes C++, C, OpenCL, Linux, Microsoft Office and more. Zhaoxin Gu has 2 emails and 1 mobile phone numbers on RocketReach.
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