Yu-Ping Wang Email & Phone Number
Senior ASIC Engineer @ Lemurian Labs
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Yu-Ping Wang Location
- California, United States
Yu-Ping Wang Work
- 2022 -now Senior ASIC Engineer @
- 2019 -2019 Senior Application Engineer @
- 2012 -2015 Staff Engineer @
- 2011 -2012 Contract Validation Engineer @
- 2004 -2010 Senior IC Design Engineer @
- 1999 -2004 Senior IC Design Engineer @
- 1996 -1999 Design Engineer @
- 1995 -1996 Design Engineer @
Yu-Ping Wang Education
- Santa Clara University
Master Of Science (Electrical Engineering)
1993-1995 - University Of California - Berkeley
Bachelor Of Science (Electrical Engineering)
1988-1993
Yu-Ping Wang Skills
- Verilog
- RTL Design
- Integrated Circuit Design
- VHDL
- Functional Verification
- Simulations
- ASIC
- Semiconductors
- Embedded Systems
- Testing
- SPI
- Serial Interfaces
- Register Files
- SoC
- Mobile Devices
- IC
- Application-Specific Integrated Circuits (ASIC)
- Logic Design
- Git
- Debugging
- Modular
- Windows
- JIRA
- Interface Design
- NCSim
- USB
- Memory Controllers
- Vector
- Arc
- Features
- Packing
- Adapter
- Design
- Chipset
- Version Control
- Integration
- Glue
- PowerPoint
- Linux
- SRAM
- MS Excel
- Data Validation
- UVM
- Timing
- IP
- English
- Engineers
- CVS
- Microsoft Office
- Silicon Validation
- Encryption
- SystemVerilog
- Documentation
- Scan
- Hardware
- JTAG
- Laboratory
- Workstations
- Controllers
- DFT
- Sensors
- Eeprom
- Collaboration Tools
- Compression
- Modifications
- Tetramax
- FPGA
- Perforce
- Effing Package Management
- House
- Unix
- Logic Analyzer
- I2C
- Flash Memory
- Confluence
- Test Coverage
- Data Management
- Interfaces
- Cadence
- Sccs
- Analytical Skill
- Application Specific Integrated Circuits Asic
- Microelectronics
- C++
- Test Fixtures
- DBMS
- Application Specific Integrated Circuits
Yu-Ping Wang Summary
- Yu-Ping Wang, based in California, United States, is currently a Senior ASIC Engineer at Lemurian Labs. Yu-Ping Wang brings experience from previous roles at Agnisys Inc, SK Hynix Memory Solutions, Intel Corporation and UPEK. Yu-Ping Wang holds a 1993 - 1995 Master Of Science in Electrical Engineering @ Santa Clara University. With a robust skill set that includes Verilog, RTL Design, Integrated Circuit Design, VHDL, Functional Verification and more. Yu-Ping Wang has 3 emails on RocketReach.
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