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Yu-Han Hung Location
Cupertino, CA, US
Yu-Han Hung Work
2017 -now Design Verification Engineer @
2013 -2017 ASIC Verification Engineer @
Yu-Han Hung Education
Northwestern University
M.S (Electrical Engineering & Computer Science)
2011-2012
University of Florida
Exchange Student (Electrical & Computer Science)
2010-2011
National Chao Tung University
B.S (Transportation Technology & Management)
2006-2010
Yu-Han Hung Skills
Universal Verification Methodology (UVM)
System Verilog
C++
Python (Programming Language)
Verilog
Yu-Han Hung Summary
Yu-Han Hung, based in Cupertino, CA, US, is currently a Design Verification Engineer at Apple. Yu-Han Hung brings experience from previous roles at Marvell Semiconductor. Yu-Han Hung holds a 2011 - 2012 M.S in Electrical Engineering & Computer Science @ Northwestern University. With a robust skill set that includes Universal Verification Methodology (UVM), System Verilog, C++, Python (Programming Language), Verilog and more. Yu-Han Hung has 3 emails and 1 mobile phone numbers on RocketReach.
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