Youssef E. Email
Principal Engineer @ EDGE
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Youssef E. Location
- Canada
Youssef E. Work
- 2024 -now Principal Engineer @
- 2023 -2024 ASIC Digital Designer-Staff Engineer (Solution Group) @
- 2022 -2023 Senior FPGA Designer @
- 2021 -2022 FPGA-HW Engineer senior consultant. @
- 2019 -2020 Senior Engineering Consultant @
- 2017 -2019 FPGA Design Specialist (Consultant @ Thales Canada Avionics) @
- 2017 -2019 Founder @ DigiLabs-MTL.ca
- 2016 -2019 Founder @ FPGA Academy
- 2015 -2016 Hardware and Software Engineering (Contract) @
- 2014 -2016 Project Manager and Design Engineering @ MicroPro R&D
- 2013 -2014 FPGA Designer (Contract) @
- 2011 -2012 IC Physical Design Engineer (Consultant) @
- 2010 -2011 Project Leader and MVP Senior Design Engineer (CDI) @
- 2009 -2010 FPGA Designer (Contract) @
- 2010 -2010 Design engineer @
- 2003 -2009 Cours Laboratory Monitoring @
- 2007 -2008 Microelectronics Research Assistant @
- 2006 -2006 Microelectronics Engineering (Internship) @
- 2012 -2013 ASIC and FPGA Digital Design Engineer - Self employed @ MicroPro R&D
Youssef E. Education
- Polytechnique Montréal
DESS (Electrical/Electronic Engineering)
2009-2017 - UQAM | Université du Québec à Montréal
Engineering Bachelor (Microelectronics)
2003-2008 - UQAM | Université du Québec à Montréal
Certificate (Telecommunication)
2002-2003 - Institut Spécialisée de Technologies Appliquées
Technicien Spécialisé (Systèmes d'Informations)
1999-2001 - École de technologie supérieure
Higher studies diploma (Engineering projects managment)
2017
Youssef E. Skills
- FPGA
- Verilog & VHDL
- ModelSim simulation tools
- Static Timing Analysis : Synopsys PrimeTime
- Gate Level Simulation
- Verilog
- Xilinx
- Testing
- Programming : C, C++, VB, VBA, ...
- Design Synthesis : Synopsys DC, Xilinx ISE, ...
- Place and Route : Encounter, Olympus, ...
- Microsoft Office
- ASIC
- Scripting: sh, Makefile, Python, cmd, ...
- PSL - Formal Verification
- SignOff
- Formal Verification
- Graphic Design : AutoCAD, DesignInsight, ...
- I2C
- Physical Design
- Device Drivers
- Simulink Embeded coder
- Matlab Coder
- Matlab GUIDE
- STM32 Microprocessors
- Field-Programmable Gate Arrays (FPGA)
- Olympus
- Cmd
- Field Programmable Gate Arrays Fpga
- Lorawan
- Encounter
- Design Synthesis
- Iot Iternet Of Thinks
- C
- AutoCAD
- Graphic Design
- Psl
- VB
- Xilinx ISE
- Place And Route
- Designinsight
- Programming
- Application Specific Integrated Circuits Asic
- VBA
- C++
- Makefile
- Synopsys Primetime
- Scripting
- Python
- Design
- Static Timing Analysis
- Synopsys Dc
- R&D
- Verilog And Vhdl
Youssef E. Summary
- Youssef E., based in Canada, is currently a Principal Engineer at EDGE. Youssef E. brings experience from previous roles at Synopsys Inc, Comtech Telecommunications Corp., Akka Technologies and Sondrel Ltd. Youssef E. holds a 2009 - 2017 DESS in Electrical/Electronic Engineering @ Polytechnique Montréal. With a robust skill set that includes FPGA, Verilog & VHDL, ModelSim simulation tools, Static Timing Analysis : Synopsys PrimeTime, Gate Level Simulation and more. Youssef E. has 1 emails on RocketReach.
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