Yorgos Blanas Email
Digital Design Engineer @ Vtool - Smart Verification
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Yorgos Blanas Location
- Gdańsk, PL
Yorgos Blanas Work
- Digital Design Engineer @ (April 2026 - Present)
- Senior Digital Design Engineer @ (April 2025 - March 2026)
- Hardware Engineer @ (July 2024 - April 2025)
- FPGA Design Application Engineer @ (February 2023 - June 2024)
- Digital IC Design Engineer @ (September 2021 - January 2023)
- Digital IC Design Engineer @ (April 2019 - August 2021)
- Graduate Digital IC Design Engineer @ (February 2018 - March 2019)
- Research and Informatics Office Assistant @ 71st Airmobile Brigade "Pontus" (February 2017 - October 2017)
- Teaching assistant @ Computer Engineering And Informatics Department (CEID), University of Patras (February 2014 - July 2014)
Yorgos Blanas Education
- University of Patras
Master's degree (Computer Engineering and Informatics Department)
2011-2016 - 1st High School of Stavroupoli, Thessaloniki 2007-2010
Yorgos Blanas Skills
- Assembly Language
- Automatic Test Pattern Generation (ATPG)
- C
- C++
- Cascading Style Sheets (CSS)
- Computer Architecture
- Embedded C
- HTML
- Java
- Linux
- Logic Design
- Logic Synthesis
- Matlab
- Military Experience
- PHP
- Python
- SQL
- Synopsys tools
- Unix
- VHDL
- Verilog
- Video Editing
Yorgos Blanas Summary
- Yorgos Blanas, based in Gdańsk, PL, is currently a Digital Design Engineer at Vtool - Smart Verification. Yorgos Blanas brings experience from previous roles at Codasip, Intel Corporation and Renesas Electronics. Yorgos Blanas holds a 2011 - 2016 Master's degree in Computer Engineering and Informatics Department @ University of Patras. With a robust skill set that includes Assembly Language, Automatic Test Pattern Generation (ATPG), C, C++, Cascading Style Sheets (CSS) and more.
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