Ying Li Email
技术副总裁 @ JL Semi Singapore Pte Ltd
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Ying Li Location
- Shanghai, CN
Ying Li Work
- 2023 -now 技术副总裁 @
- 2020 -2023 硬件研发副总裁 @
- 2018 -2020 研发总监 @
- 2015 -2018 Director @
- 2014 -2015 Architect @
- 2012 -2014 Staff SoC R and D Design Engineer @
- 2010 -2012 Principle Design Engineer @
- 2009 -2012 Technical Manager @
- 2007 -2009 Lead Design Engineer @
- 2006 -2007 SPS senior consultant @
- 2005 -2006 Senior Design engineer @
- 2004 -2005 Senior Design engineer @ IPCore
- 2001 -2004 Senior Design engineer @
- 1994 -1998 Engineer @
Ying Li Education
- 上海交通大学
Master of Engineering (M.Eng.) (EE)
1998-2001 - Shanghai Jiao Tong University
bachelor of applied maths (applied mathmatics)
1992-1994 - Shanghai Jiao Tong University
Bachelor of Engineering (BEng), EE (EE)
1990-1994
Ying Li Skills
- SoC
- EDA
- ASIC
- Static Timing Analysis
- Verilog
- TCL
- IC
- RTL design
- Semiconductors
- SystemVerilog
- Low-power Design
- FPGA
- VLSI
- Functional Verification
- Timing Closure
- Physical Design
- Perl
- Mixed Signal
- Logic Design
- Application-Specific Integrated Circuits (ASIC)
- System on a Chip (SoC)
- Integrated Circuits (IC)
- Engineering
- Design
- Integrated Circuits Ic
- Software Development
- IP
- Cadence
- Management
- Microsoft Excel
- Project Management
- Application Specific Integrated Circuits Asic
- System on a Chip Soc
- R&d
- Sales
- Low Power Design
- Customer Service
- Application Specific Integrated Circuits
- System on a Chip
- Integrated Circuits
Ying Li Summary
- Ying Li, based in Shanghai, CN, is currently a 技术副总裁 at 景略半导体（上海）有限公司. Ying Li brings experience from previous roles at 沐曦集成电路有限公司, 景略半导体（上海）有限公司 and 铿腾设计系统公司. Ying Li holds a 1998 - 2001 Master of Engineering (M.Eng.) in EE @ 上海交通大学. With a robust skill set that includes SoC, EDA, ASIC, Static Timing Analysis, Verilog and more. Ying Li has 1 emails on RocketReach.
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