Yashpreet Kaur Email & Phone Number
Sr. PMTS Silicon Design Engineer and Manager @ AMD
5 free lookup(s).
If you need more lookups,
subscriptions start at $34 USD/month.
Yashpreet Kaur Location
- Santa Clara, CA, US
Yashpreet Kaur Work
- Sr. PMTS Silicon Design Engineer and Manager @ (August 2026 - Present)
- IP Logic Design and Micro-architecture @ (January 2025 - July 2026)
- FPGA IP Design Manager @ (October 2019 - December 2023)
- Sr. IP Design Engineer @ (February 2014 - October 2019)
- Sr. SoC Design Engineer @ (February 2012 - March 2014)
- SoC Design Engineer @ (August 2008 - February 2012)
Yashpreet Kaur Education
- University of Southern California
Master of Science - MS (Electrical Engineering)
2006-2008
Yashpreet Kaur Skills
- VLSI
- Logic Design
- Computer Architecture
- Digital Electronics
- RTL design
- Debugging
- Static Timing Analysis
- Logic Synthesis
- Soc interconnect Fabric
- SystemVerilog
- ASIC
- SoC
- Verilog
- Application Specific Integrated Circuits Asic
- FPGA
- Very Large Scale Integration Vlsi
- System On A Chip Soc
- Very Large Scale Integration
- System on a Chip
- Application Specific Integrated Circuits
Yashpreet Kaur Summary
- Yashpreet Kaur, based in Santa Clara, CA, US, is currently a Sr. PMTS Silicon Design Engineer and Manager at AMD. Yashpreet Kaur brings experience from previous roles at Intel Corporation and Altera. Yashpreet Kaur holds a 2006 - 2008 Master of Science - MS in Electrical Engineering @ University of Southern California. With a robust skill set that includes VLSI, Logic Design, Computer Architecture, Digital Electronics, RTL design and more. Yashpreet Kaur has 1 emails and 2 mobile phone numbers on RocketReach.
Looking for a different Yashpreet Kaur?
Find contact details for 700 million professionals.
G2 Crowd Trusted
300K+ Plugin Users
© 2026 RocketReach.co