Yashaswini Rl's Location
Sunnyvale, CA, US
Yashaswini Rl's Work
- Design Verification Engineer @ Apple
- Senior Design Verification Engineer @ Samsung India
- Pre-silicon Validation Engineer @ Intel Capital
- Intern @ Intel Capital
- Intern Engineer @ Indian Institute of Science (IISc)
Yashaswini Rl's Education
- University of Massachusettes, Amherst
Master of Science (M.S.) (Electrical and Electronics Engineering)
2013 - 2015 - B. M. S. College of Engineering
Bachelor of Engineering (B.E.) (Electrical, Electronics and Communications Engineering)
2009 - 2013
Yashaswini Rl's Skills
- PowerPoint
- Cadence Virtuoso
- Linux
- Algorithms
- 8051 Microcontroller
- C
- Computer Hardware
- Perl Script
- Windows
- Perl
Yashaswini Rl's Summary
Yashaswini Rl, based in Sunnyvale, CA, US, is currently a Design Verification Engineer at Apple, bringing experience from previous roles at Samsung Electronics, Intel Corporation and Indian Institute of Science. Yashaswini Rl holds a 2013 - 2015 Master of Science (M.S.) in Electrical and Electronics Engineering @ University of Massachusettes, Amherst. With a robust skill set that includes PowerPoint, Cadence Virtuoso, Linux, Algorithms, 8051 Microcontroller and more, Yashaswini Rl contributes valuable insights to the industry. Yashaswini Rl has 3 emails on RocketReach.
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