Yajun Ran's Location
San Jose, CA, US
Yajun Ran's Work
- CPU design engineer @ Apple
- Sr. Hardware Engineer @ NVIDIA
- Member of Consulting Staff, Project Leader @ Cadence Design Systems
- Sr. R and D Engineer @ Clear Shape Technologies , Inc.
- Intern in PrimeTime Group @ Synopsys Inc
- Intern in CadMos Group @ Cadence Design Systems
- Intern in Physical Compiler Group @ Synopsys Inc
Yajun Ran's Education
- UC Santa Barbara
Ph.D.
2000 - 2005 - Peking University1992 - 2000
Yajun Ran's Skills
- Accredited Training
- Hardware Architecture
- Hardware Design
- Physical Design
- Automation
Yajun Ran's Summary
Yajun Ran, based in San Jose, CA, US, is currently a CPU design engineer at Apple, bringing experience from previous roles at NVIDIA, Cadence Design Systems, Clear Shape Technologies and Synopsys. Yajun Ran holds a 2000 - 2005 Ph.D. @ UC Santa Barbara. With a robust skill set that includes Accredited Training, Hardware Architecture, Hardware Design, Physical Design, Automation and more, Yajun Ran contributes valuable insights to the industry. Yajun Ran has 1 email on RocketReach.
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