Xiaomeng Liu Location
Shanghai, CN
Xiaomeng Liu Work
- 2018 - now ASIC Design Verification Engineer @ Synopsys Inc
- 2016 - 2018 ASIC Design Verification Engineer @ Brite Semiconductor
- 2015 - 2016 Lead Design Engineer @ Cadence Design Systems
- 2012 - 2015 ASIC Design Verification Engineer @ Qualcomm
- 2010 - 2011 Intern ASIC Engineer @ 中娱半导体
Xiaomeng Liu Education
- Southeast University
硕士 (微电子与固体电子学)
2009 - 2011 - Hefei University of Technology
学士 (应用物理)
2003 - 2007
Xiaomeng Liu Skills
- SystemVerilog
- SoC
- Java
- Project Management
- Hbm
- Photoshop
- ASIC
- UVM
- Debugging
- Leadership
Xiaomeng Liu Summary
Xiaomeng Liu, based in Shanghai, CN, is currently a ASIC Design Verification Engineer at Synopsys Inc. Xiaomeng Liu brings experience from previous roles at Brite Semiconductor, Cadence Design Systems, Qualcomm and 中娱半导体. Xiaomeng Liu holds a 2009 - 2011 硕士 in 微电子与固体电子学 @ Southeast University. With a robust skill set that includes SystemVerilog, SoC, Java, Project Management, Hbm and more. Xiaomeng Liu has 1 emails on RocketReach.
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