Staff Engieer, Engineering Project Lead @ (November 2021 - December 2024)
ASIC Verification Engineer, Sr II @ (November 2020 - October 2021)
ASIC Verification Engineer, Sr I @ (January 2019 - October 2020)
ASIC Verification Engineer @ (November 2016 - December 2018)
Design Verification Engineer Intern @ (March 2016 - July 2016)
Instructional Student Assistant and Teaching Assistant @ (January 2015 - June 2015)
Xiaochen Zhang Education
San Jose State University
M.S (Electrical Engineering)
2012-2015
Huazhong University of Science and Technology
B.S (Electrical Engineering)
2006-2010
Xiaochen Zhang Skills
Synopsys Vcs
Microsoft Word
Research
Spyglass
Cadence Encounter
OpenMP
FPGA
Synopsys Primetime
Eclipse
Xilinx ISE
Electronics
Cadence Virtuoso
Microcontrollers
Microsoft Visual Studio C++
Project Management
GUI test automation
Teaching
Computer Architecture
Hardware
C
Verilog
Synopsys tools
Perl
Computer Hardware
Matlab
SystemVerilog
PowerPoint
C++
Parallel Computing
Embedded Systems
Unix
Mentor Graphics Questa
ASIC
Altera Quartus
Shell Scripting
VHDL
Python
Xiaochen Zhang Summary
Xiaochen Zhang, based in Eindhoven, NB, NL, is currently a Sr Staff Engineer, Project Enigeering Management at Synopsys Inc. Xiaochen Zhang brings experience from previous roles at Synopsys Inc. Xiaochen Zhang holds a 2012 - 2015 M.S in Electrical Engineering @ San Jose State University. With a robust skill set that includes Synopsys Vcs, Microsoft Word, Research, Spyglass, Cadence Encounter and more. Xiaochen Zhang has 1 emails and 1 mobile phone numbers on RocketReach.
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