Xi Luo Email & Phone Number
SMTS Silicon Design Engineer @ AMD
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Xi Luo Location
- San Diego, CA, US
Xi Luo Work
- SMTS Silicon Design Engineer @ (June 2024 - Present)
- Staff Engineer - System Cache RTL design @ (November 2020 - June 2024)
- Senior Engineer - System Cache RTL Design @ (December 2016 - November 2020)
- ASIC Design Engineer - Custom Implementation @ (November 2014 - November 2016)
- Student @ (September 2012 - March 2014)
- Circuit Designer @ Integrated Circuit Laboratory of Tsinghua University (July 2013 - August 2013)
- Teaching assistant @ (January 2010 - May 2012)
Xi Luo Education
- UCLA
Master of Science - MS (Electrical and Electronics Engineering)
2012-2014 - Purdue University
B.S (Electrical Engineering)
2008-2012
Xi Luo Summary
- Xi Luo, based in San Diego, CA, US, is currently a SMTS Silicon Design Engineer at AMD. Xi Luo brings experience from previous roles at Qualcomm and UCLA. Xi Luo holds a 2012 - 2014 Master of Science - MS in Electrical and Electronics Engineering @ UCLA. Xi Luo has 3 emails and 5 mobile phone numbers on RocketReach.
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