Xi Luo Email & Phone Number
SMTS - SerDes Application and Validation Engineer @ AMD
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Xi Luo Location
- San Jose, CA, US
Xi Luo Work
- 2023 -now SMTS - SerDes Application and Validation Engineer @
- 2022 -2023 Silicon Validation Engineer @
- 2020 -2022 Validation Engineering Manager @
- 2020 -2020 Member of Technical Staff - SerDes Application Engineer @
- 2017 -2020 Senior Engineer 2 @
- 2015 -2017 Senior Engineer 1 @
- 2011 -2015 Senior Product Engineer @
- 2008 -2009 Product Engineering Intern @
Xi Luo Education
- Stanford University
Master of Science - MS (Electrical and Electronics Engineering)
- University of Toronto
Bachelor of Applied Science - BASc (Electrical and Electronics Engineering)
Xi Luo Skills
- Field Programmable Gate Arrays Fpga
- C
- Debugging
- HSPICE
- Perl
- Matlab
- PCIe
- ASIC
- Electronics
- Compliance Testing
- Verilog
- Cadence
- TCL
- Characterization
- Microsoft Office
- Java
- Embedded Systems
- Testing
- SERDES
- FPGA
- SoC
- PHP
- C++
- ModelSim
- Failure Analysis
- SQL
- Python
- Semiconductors
- Simulations
- MySQL
- IC
- Field Programmable Gate Arrays
Xi Luo Summary
- Xi Luo, based in San Jose, CA, US, is currently a SMTS - SerDes Application and Validation Engineer at AMD. Xi Luo brings experience from previous roles at Meta, Groq and Xilinx. Xi Luo holds a Master of Science - MS in Electrical and Electronics Engineering @ Stanford University. With a robust skill set that includes Field Programmable Gate Arrays Fpga, C, Debugging, HSPICE, Perl and more. Xi Luo has 2 emails and 2 mobile phone numbers on RocketReach.
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