Xi Luo Email & Phone Number
SMTS - SerDes Application and Validation Engineer @ AMD
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Xi Luo Location
- San Jose, CA, US
Xi Luo Work
- SMTS - SerDes Application and Validation Engineer @ (August 2023 - Present)
- Silicon Validation Engineer @ (April 2022 - August 2023)
- Validation Engineering Manager @ (December 2020 - April 2022)
- Member of Technical Staff - SerDes Application Engineer @ (May 2020 - November 2020)
- Senior Engineer 2 @ (May 2017 - May 2020)
- Senior Engineer 1 @ (November 2015 - May 2017)
- Senior Product Engineer @ (March 2011 - November 2015)
- Product Engineering Intern @ (June 2008 - July 2009)
Xi Luo Education
- University of Toronto
Bachelor of Applied Science - BASc (Electrical and Electronics Engineering)
- Stanford University
Master of Science - MS (Electrical and Electronics Engineering)
Xi Luo Skills
- C
- C++
- Characterization
- Compliance Testing
- Debugging
- Electronics
- FPGA
- Failure Analysis
- Field-Programmable Gate Arrays (FPGA)
- Matlab
- ModelSim
- PCIe
- Perl
- Python
- Semiconductors
- SerDes
- TCL
- Testing
- Verilog
- Field Programmable Gate Arrays Fpga
- HSPICE
- ASIC
- Cadence
- Microsoft Office
- Java
- Embedded Systems
- SoC
- PHP
- SQL
- Simulations
- MySQL
- IC
- Field Programmable Gate Arrays
Xi Luo Summary
- Xi Luo, based in San Jose, CA, US, is currently a SMTS - SerDes Application and Validation Engineer at AMD. Xi Luo brings experience from previous roles at Meta, Groq and Xilinx. Xi Luo holds a Bachelor of Applied Science - BASc in Electrical and Electronics Engineering @ University of Toronto. With a robust skill set that includes C, C++, Characterization, Compliance Testing, Debugging and more. Xi Luo has 2 emails and 2 mobile phone numbers on RocketReach.
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