William Phan Email & Phone Number
Principal Hardware Design and Verification Engineer @ Western Digital
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William Phan Location
- San Jose, CA, US
William Phan Work
- Principal Hardware Design and Verification Engineer @ (November 2015 - Present)
- Senior Hardware Design and Verification Engineer @ (February 2004 - October 2015)
- Hardware Design and Verification Engineer @ IBM (June 1997 - January 2004)
William Phan Education
- San José State University
BS (Computer Engineer)
1993-1997
William Phan Skills
- ASIC
- Altera Quartus
- C
- C++
- Debugging
- FPGA
- Hardware
- Hardware Design
- Logic Analyzer
- Microcontrollers
- ModelSim
- RTL design
- Simulation
- Storage
- SystemVerilog
- VHDL
- VLSI
- Verilog
- Xilinx
William Phan Summary
- William Phan, based in San Jose, CA, US, is currently a Principal Hardware Design and Verification Engineer at Western Digital. William Phan brings experience from previous roles at Hitachi GST and IBM. William Phan holds a 1993 - 1997 BS in Computer Engineer @ San José State University. With a robust skill set that includes ASIC, Altera Quartus, C, C++, Debugging and more. William Phan has 1 emails and 2 mobile phone numbers on RocketReach.
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