Weiwei Jin Email
Staff, SOC Engineer @ Synopsys Inc
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Weiwei Jin Location
- Beijing, China
Weiwei Jin Work
- Staff, SOC Engineer @ (September 2020 - Present)
- Senior Physical Design Engineer @ (March 2012 - August 2020)
- IP Core Design Engineer @ SicMicro (October 2010 - March 2012)
- IC Design Engineer @ Telegene (August 2007 - September 2010)
- Chip Design Engineer @ TSMC (January 2005 - January 2007)
Weiwei Jin Education
- Tsinghua University
Master (Microelectronics)
2002-2005 - Hebei University of Technology
BS (Electronic Engineer)
1998-2002
Weiwei Jin Skills
- SystemVerilog
- Physical Design
- Design
- IC
- ASIC
- Logic Design
- SoC
- Verilog
- VLSI
- Lower Power Design
- Consumer Electronics
- Debugging
- TCL
- Timing Closure
- Perl
- RTL design
Weiwei Jin Summary
- Weiwei Jin, based in Beijing, China, is currently a Staff, SOC Engineer at Synopsys Inc. Weiwei Jin brings experience from previous roles at Nufront, SicMicro, Telegene and TSMC. Weiwei Jin holds a 2002 - 2005 Master in Microelectronics @ Tsinghua University. With a robust skill set that includes SystemVerilog, Physical Design, Design, IC, ASIC and more. Weiwei Jin has 2 emails on RocketReach.
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