Weiwei Jin Email
Staff, SOC Engineer @ Synopsys Inc
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Weiwei Jin Location
- Beijing, China
Weiwei Jin Work
- 2020 -now Staff, SOC Engineer @
- 2012 -2020 Senior Physical Design Engineer @
- 2010 -2012 IP Core Design Engineer @ SicMicro
- 2007 -2010 IC Design Engineer @ Telegene
- 2005 -2007 Chip Design Engineer @ TSMC
Weiwei Jin Education
- Tsinghua University
Master (Microelectronics)
2002-2005 - Hebei University of Technology
BS (Electronic Engineer)
1998-2002
Weiwei Jin Skills
- SystemVerilog
- Physical Design
- Design
- IC
- ASIC
- Logic Design
- SoC
- Verilog
- VLSI
- Lower Power Design
- Consumer Electronics
- Debugging
- TCL
- Timing Closure
- Perl
- RTL design
Weiwei Jin Summary
- Weiwei Jin, based in Beijing, China, is currently a Staff, SOC Engineer at Synopsys Inc. Weiwei Jin brings experience from previous roles at Nufront, SicMicro, Telegene and TSMC. Weiwei Jin holds a 2002 - 2005 Master in Microelectronics @ Tsinghua University. With a robust skill set that includes SystemVerilog, Physical Design, Design, IC, ASIC and more. Weiwei Jin has 2 emails on RocketReach.
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