Weili Chen Email
Analog Mixed Signal IC Layout Design @ Synopsys Inc
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Weili Chen Location
- Toronto, ON, CA
Weili Chen Work
- 2025 -now Analog Mixed Signal IC Layout Design @
- 2016 -2025 HiSilicon @ HiSilicon
- 2012 -2016 Senior Member of Technical Staff, Physical Design @
- 2004 -2012 Sr IC Layout Designer @ AMD/ATI
- 2002 -2004 Sr RFIC Layout Engineer @ Sirific Wireless
- 2000 -2002 Layout Designer @ Quake Technologies/AMCC
Weili Chen Education
- Yanshan University
M.Sc (Electrical Engineering)
- Carleton University
(VLSI Design)
Weili Chen Skills
- Cadence Virtuoso
- Mixed Signal
- Analog
- CMOS
- DRC
- Layout
- LVS
- IC
- Silicon
- PLL
- Physical Design
- EDA
- Floorplanning
- VLSI
- ESD control
- RF circuits
- Physical Verification
- Calibre
- ESD
- Parasitic Extraction
- BiCMOS
- Pcell Development
- FINFET layout
- High Speed Layout
- Integrated Circuits (IC)
- PMO
- Structures
- Reliability
- Interfaces
- Integrated Circuits Ic
- Program Management
- Semiconductors
- Management
- Design
- Integrated Circuits
Weili Chen Summary
- Weili Chen, based in Toronto, ON, CA, is currently a Analog Mixed Signal IC Layout Design at Synopsys Inc. Weili Chen brings experience from previous roles at HiSilicon, Semtech Snowbush IP/Rambus, AMD/ATI and Sirific Wireless. Weili Chen holds a M.Sc in Electrical Engineering @ Yanshan University. With a robust skill set that includes Cadence Virtuoso, Mixed Signal, Analog, CMOS, DRC and more. Weili Chen has 1 emails on RocketReach.
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