Retired @ From Avago (November 2014 - August 2017)
Principal Engineer @ (January 1999 - January 2007)
Member of the technical staff @ AT&T/Lucent/Agere Systems (January 1995 - January 2007)
Project Team Leader @ ATI Research Inc (August 1998 - January 1999)
Member of the Technical Staff @ Lucent Technologies (April 1995 - August 1998)
Leading Engineer @ Integrated Circuit Systems (January 1993 - March 1995)
senior engineer @ Integrated Circuit Systems (January 1992 - January 1995)
Vlad Sindalovsky Education
Leningrad Electro-Technical Institute 1965-1971
College for Electronic Engineers St
MSEE
Vlad Sindalovsky Skills
High speed digital design for SAS, SATA, PCIe SerDes applications.
Mixed signal design modeling and verification.
Mixed Signal
SERDES
Microprocessors
Verilog
IC
SoC
Static Timing Analysis
Simulations
ASIC
Low-power Design
VLSI
Integrated Circuit Design
RTL design
Analog
CMOS
VHDL
Semiconductors
Logic Synthesis
Debugging
Circuit Design
C
PCIe
EDA
System on a Chip (SoC)
Strategy
Pcie Serdes Applications
Mixed Signal Design Modeling and Verification
High Speed Digital Design for Sas
SATA
SQL
Software Development
Testing
Low Power Design
System on a Chip Soc
System on a Chip
Vlad Sindalovsky Summary
Vlad Sindalovsky, based in Pennsylvania, United States, is currently a Principal Engineer at LSI. Vlad Sindalovsky brings experience from previous roles at LSI (formally Agere Systems), From Avago, Lucent Technologies and AT&T/Lucent/Agere Systems. Vlad Sindalovsky holds a 1965 - 1971 Leningrad Electro-Technical Institute. With a robust skill set that includes High speed digital design for SAS, SATA, PCIe SerDes applications., Mixed signal design modeling and verification., Mixed Signal, SERDES, Microprocessors and more. Vlad Sindalovsky has 1 emails and 1 mobile phone numbers on RocketReach.
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