Vlad Sergeyev Email
Hardware Design Manager @ Perle Systems
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Vlad Sergeyev Location
- Mississauga, ON, CA
Vlad Sergeyev Work
- 2019 -now Hardware Design Manager @
- 2015 -2019 Sr. Electronics Designer @
- 2006 -2015 Sr. Electronics Designer @
- 2002 -2006 Electrical Engineer @ Integrity Testing Laboratory Inc
- 2000 -2002 Senior Hardware Engineer, Team Lead @ Enterprise "OM”
- 1994 -2000 Senior Hardware Engineer, Team Lead @ Odessa Scientific-Research Institute of Television
- 1987 -1994 Hardware Engineer @ Odessa Scientific-Research Institute of Television
Vlad Sergeyev Education
- Ryerson University
Master of Engineering (M.Eng.) (Electrical and Computer Engineering)
2005-2010 - Odessa Polytechnic National University
Bachelor of Science (B.Sc.) (Electrical Engineering)
1982-1987
Vlad Sergeyev Skills
- Kinetis
- STM32
- MSP430
- 8051
- ARM
- AVR
- FPGA
- CPLD
- Tiger Shark DSP
- ASIC
- PCIe
- LPC bus
- ISA bus
- JTAG
- I2C
- SPI
- CAN
- UART
- USB
- Ethernet
- Altium Designer
- OrCAD Capture CIS
- OrCAD Layout
- PSpice
- LTSpice
- Xilinx IDE
- Altera Quartus
- Synopsys tools
- Allegro
- ModelSim
- AutoCAD
- Solidworks
- C/C++
- Assembler
- Visual Basic
- Python
- Verilog
- VHDL
- SystemC
Vlad Sergeyev Summary
- Vlad Sergeyev, based in Mississauga, ON, CA, is currently a Hardware Design Manager at Perle Systems. Vlad Sergeyev brings experience from previous roles at Teknoscan Systems Inc., Smiths Detection, Integrity Testing Laboratory Inc and Enterprise "OM”. Vlad Sergeyev holds a 2005 - 2010 Master of Engineering (M.Eng.) in Electrical and Computer Engineering @ Ryerson University. With a robust skill set that includes Kinetis, STM32, MSP430, 8051, ARM and more. Vlad Sergeyev has 2 emails on RocketReach.
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