Sr. Engineering Manager @ (November 2014 - December 2023)
ASIC Staff Engineer @ (December 2012 - November 2014)
Engineering Specialist @ (September 2011 - December 2012)
Technical Leader @ STMicroelecronics (August 2008 - August 2011)
Senior Design Engineer @ (April 2007 - July 2008)
Member Of Technical Staff (MTS) @ (April 2006 - April 2007)
Design Engg. @ Texas Instruments (January 2004 - April 2006)
Vivek Seth Education
Institute of Management Technology, Ghaziabad
PGEM (General Management)
2011-2012
Indian Institute of Technology (Banaras Hindu University), Varanasi
B.Tech (Electrical)
1999-2003
LDD
Vivek Seth Skills
Static Timing Analysis
ASIC
Physical Design
SoC
IC
Primetime
TCL
VLSI
EDA
Logic Synthesis
Timing Closure
Cadence
Signal Integrity
Project Management
SOC implementation
Physical Verification
RTL design
Design
Vivek Seth Summary
Vivek Seth, based in Bengaluru, KA, IN, is currently a Sr. Manager Silicon Design Engineering at AMD. Vivek Seth brings experience from previous roles at Intel Corporation, LSI Corporation, STMicroelectronics and STMicroelecronics. Vivek Seth holds a 2011 - 2012 PGEM in General Management @ Institute of Management Technology, Ghaziabad. With a robust skill set that includes Static Timing Analysis, ASIC, Physical Design, SoC, IC and more. Vivek Seth has 2 emails and 1 mobile phone numbers on RocketReach.
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