Vinod Reddy Email & Phone Number
Hardware Engineering Tech Lead @ Cisco
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Vinod Reddy Location
- San Jose, CA, US
Vinod Reddy Work
- 2022 -now Hardware Engineering Tech Lead @
- 2020 -2022 IP Design Engineer @
- 2018 -2020 IP Design Engineer @
- 2015 -2018 Application Engineer @
- 2012 -2015 Application Engineer @ Altera
- 2011 -2012 Design and Verification Engineer (Contractor) @
Vinod Reddy Education
- San José State University
Masters (• Worked as Volunteer in INTEL ISEF (International Science & Engineering Fair) at San jose, CA, May 2010. • Worked as Volunteer in Embedded Conference 2009 at San jose, CA.)
2008-2010 - Princeton college of Engnieerning and Technology
Bachelor's degree (Electrical, Electronics and Communications Engineering)
2004-2007
Vinod Reddy Skills
- Verilog
- VHDL
- Cadence Virtuoso
- Unix Administration
- Hardware Verification
- Troubleshooting
- Perl
- Static Timing Analysis
- RTL design
- CDC
- FPGA
- ASIC
- I2C
- I2S
- SPI
- RMI
- TCP/IP
- UDP
- C
- Mixed Signal
- Digital Hardware Design
- ModelSim
- Xilinx
- Windows
- Operating Systems
- English
- Linux
- Compilers
- Unix
- Matlab
- Hardware
- VCS
- Scripting
- Altera
- NC-Verilog
- RTL coding
- Solaris
- EDA
- VLSI
- DFT
- Timing Closure
- Digital Design
- Functional Verification
- PCIe
- Spectre
- Labview
- Programming
- C++
- Nc Verilog
Vinod Reddy Summary
- Vinod Reddy, based in San Jose, CA, US, is currently a Hardware Engineering Tech Lead at Cisco. Vinod Reddy brings experience from previous roles at Intel Corporation and Altera. Vinod Reddy holds a 2008 - 2010 Masters in • Worked as Volunteer in INTEL ISEF (International Science & Engineering Fair) at San jose, CA, May 2010. • Worked as Volunteer in Embedded Conference 2009 at San jose, CA. @ San José State University. With a robust skill set that includes Verilog, VHDL, Cadence Virtuoso, Unix Administration, Hardware Verification and more. Vinod Reddy has 2 emails and 2 mobile phone numbers on RocketReach.
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