Vinod Bhat Email & Phone Number
ASIC Design Manager @ Meta
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Vinod Bhat Location
- San Jose, CA, US
Vinod Bhat Work
- 2022 -now ASIC Design Manager @
- 2020 -2022 SoC Platform Architecture Program Manager @
- 2017 -2020 Engineering Manager, Artificial Intelligence Product Group @
- 2014 -2017 Director, IC Design @
- 2013 -2014 Senior IC Design Manager @
- 2012 -2013 IC Design Manager @
- 2011 -2012 Senior ASIC Design Engineer @ NVIDIA
- 2010 -2011 Member of Technical Staff @
- 2002 -2010 Senior ASIC Design Engineer @
Vinod Bhat Education
- Stanford University
MS (EE)
2000-2002 - Indian Institute of Technology, Bombay
B Tech (Electrical Engineering)
1996-2000
Vinod Bhat Skills
- RTL design
- SoC
- Verilog
- Algorithms
- ASIC
- Static Timing Analysis
- Computer Architecture
- Logic Synthesis
- Primetime
- Timing Closure
- VLSI
- Processors
- RTL
- Functional Verification
- Low-power Design
- DFT
- EDA
- Integrated Circuit Design
- Application-Specific Integrated Circuits (ASIC)
- Very-Large-Scale Integration (VLSI)
- System on a Chip (SoC)
- Management
- Ic Design
- Computer Hardware
- System on a Chip Soc
- Integrated Circuit
- Application Specific Integrated Circuits Asic
- Design
- Low Power Design
- Very Large Scale Integration Vlsi
- Asic Design
- Application Specific Integrated Circuits
- System on a Chip
- Very Large Scale Integration
Vinod Bhat Summary
- Vinod Bhat, based in San Jose, CA, US, is currently a ASIC Design Manager at Meta. Vinod Bhat brings experience from previous roles at Apple, Intel Corporation and InvenSense, Inc.. Vinod Bhat holds a 2000 - 2002 MS in EE @ Stanford University. With a robust skill set that includes RTL design, SoC, Verilog, Algorithms, ASIC and more. Vinod Bhat has 3 emails and 1 mobile phone numbers on RocketReach.
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