Vincent Au Email & Phone Number
ASIC Engineering Manager, AI Infra Silicon @ Meta
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Vincent Au Location
- San Jose, CA, US
Vincent Au Work
- ASIC Engineering Manager, AI Infra Silicon @ (February 2025 - Present)
- Technical Lead Manager, Senior Staff SOC Silicon Engineer @ (March 2022 - March 2025)
- Staff SOC Verification Engineer, Autonomous Vehicle Hardware Systems @ (December 2019 - March 2022)
- Senior Engineering Manager, Design Verification @ (November 2017 - December 2019)
- Principal Engineer and Senior Engineering Manager @ (July 2014 - November 2017)
- Technical Leader, Design Verification @ (March 2012 - June 2014)
- Senior Member Of Technical Staff @ (May 2006 - March 2012)
- Senior Hardware Engineer @ (January 2004 - May 2006)
- Verification Engineer @ (June 2001 - December 2003)
Vincent Au Education
- Stanford University
Master of Science in Electrical Engineering (Engineer)
- University of Waterloo
Bachelors of Science in Electrical Engineering (Engineering)
Vincent Au Skills
- ARM
- ASIC
- Debugging
- Embedded Systems
- Functional Verification
- H.264
- Hardware
- Mixed-Signal IC Design
- Perl
- RTL Design
- Semiconductors
- SoC
- System Architecture
- SystemVerilog
- VLSI
- Verilog
Vincent Au Summary
- Vincent Au, based in San Jose, CA, US, is currently a ASIC Engineering Manager, AI Infra Silicon at Meta. Vincent Au brings experience from previous roles at Cruise, Intel Corporation and SK hynix memory solutions inc.. Vincent Au holds a Master of Science in Electrical Engineering in Engineer @ Stanford University. With a robust skill set that includes ARM, ASIC, Debugging, Embedded Systems, Functional Verification and more. Vincent Au has 5 emails and 1 mobile phone numbers on RocketReach.
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