Vinay Teja Email
Verification Engineer VLSI @ Ampere
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Vinay Teja Location
- Bayan Lepas, MY
Vinay Teja Work
- Verification Engineer VLSI @ (May 2019 - Present)
- Technical Analyst VLSI @ (October 2017 - April 2019)
- Meber of technical staf @ Graphene Semiconductor Services Pvt Ltd. (March 2015 - October 2017)
- vlsi Senior Verification Engineer @ (July 2014 - March 2015)
- ASIC Verification Engineer @ Kacper Technologies Pvt Ltd (February 2012 - June 2014)
Vinay Teja Education
- Jawaharlal Nehru Technological University
Master of Science (M.S.) (VLSI AND EMBEDDED SYSTEMS)
2010-2012 - SLC'SIET
Bachelor of Technology (BTech) (Electronics and Communications Engineering)
2006-2010 - Jawahar Navodaya School
CBSE
2000-2004
Vinay Teja Skills
- Verilog
- C
- system verilog
- Open Verification Methodology
- UVM
- SystemVerilog
- Functional Verification
- ModelSim
- RTL design
- ASIC
- AMBA AHB
- VLSI
- Integrated Circuit Design
- VHDL
- SoC
- I2C
Vinay Teja Summary
- Vinay Teja, based in Bayan Lepas, MY, is currently a Verification Engineer VLSI at Ampere. Vinay Teja brings experience from previous roles at UST Global, Graphene Semiconductor Services Pvt Ltd., IGATE and Kacper Technologies Pvt Ltd. Vinay Teja holds a 2010 - 2012 Master of Science (M.S.) in VLSI AND EMBEDDED SYSTEMS @ Jawaharlal Nehru Technological University. With a robust skill set that includes Verilog, C, system verilog, Open Verification Methodology, UVM and more. Vinay Teja has 2 emails on RocketReach.
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