Vikram Kamath Email & Phone Number
Asic Design Engineer - Intern @ Scalable Systems Research Labs Inc.
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Vikram Kamath Location
- San Jose, California, United States
Vikram Kamath Work
- 2016 -now Asic Design Engineer - Intern @
- 2013 -2013 Systems Engineer - Intern @
- now Cpu Design Engineer @
- now Actively Looking for Full-Time Opportunities in Asic Design and Verifcation and Validation | Uvm @
Vikram Kamath Education
- San Jose State University
Masters (Communications, Engineering, Electronics)
2013-2015 - Visvesvaraya Technological University
Bachelors (Electronics, Engineering, Communications)
2008-2012
Vikram Kamath Skills
- Verilog
- VHDL
- ModelSim
- ASIC
- SystemVerilog
- C
- Algorithms
- Cadence Virtuoso
- VLSI
- Xilinx
- Circuit Design
- CMOS
- UVM
- Windows
- Public Speaking
- Teamwork
- Research
- Java
- RTL Design
- Perl
- Static Timing Analysis
- Matlab
- Functional Verification
- FPGA
- Linux
- Debugging
- SoC
- Computer Architecture
- C++
- Xilinx ISE
- Synopsys tools
- Unix
- Testing
- Physical Design
- Altera Quartus
- Assembly Language
- Formal Verification
- Timing Closure
- SQL
- Logic Design
- I2C
- Low-power Design
- EDA
- DFT
- Microsoft Office
- Programming
- Embedded Systems
- Microcontrollers
- Leadership
- Simulations
- Low Power Design
Vikram Kamath Summary
- Vikram Kamath, based in San Jose, California, United States, is currently a Asic Design Engineer - Intern at Scalable Systems Research Labs Inc.. Vikram Kamath brings experience from previous roles at Canbank Computer Services Limited and Scalable Systems Research Labs Inc.. Vikram Kamath holds a 2013 - 2015 Masters in Communications, Engineering, Electronics @ San Jose State University. With a robust skill set that includes Verilog, VHDL, ModelSim, ASIC, SystemVerilog and more. Vikram Kamath has 2 emails and 2 mobile phone numbers on RocketReach.
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