Venkat Ramesh Email
Physical Design Engineer - Full Chip Timing @ Intel Corporation
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Venkat Ramesh Location
- Santa Clara, CA, US
Venkat Ramesh Work
- Physical Design Engineer - Full Chip Timing @ (February 2019 - Present)
- Embedded Research and Development Assistant @ Digital Connections Pvt Ltd (July 2014 - August 2015)
- Apprenticeship @ Digital Connections Pvt Ltd (January 2013 - May 2013)
Venkat Ramesh Education
- Santa Clara University
Pursuing Masters (Electrical and Electronics Engineering)
2015-2017 - University of Mumbai
Bachelor’s Degree (Electrical, Electronics and Communications Engineering)
2009-2015
Venkat Ramesh Summary
- Venkat Ramesh, based in Santa Clara, CA, US, is currently a Physical Design Engineer - Full Chip Timing at Intel Corporation. Venkat Ramesh brings experience from previous roles at Digital Connections Pvt Ltd. Venkat Ramesh holds a 2015 - 2017 Pursuing Masters in Electrical and Electronics Engineering @ Santa Clara University. Venkat Ramesh has 2 emails on RocketReach.
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